Forum Discussion

JKuba2's avatar
JKuba2
Icon for New Contributor rankNew Contributor
5 years ago

BUG REPORT: VHDL 2008 target aggregate assignment leads to missing driver Warning

Hello, I'm using target aggregates in VHDL 2008 and I found out, that Quartus (specifically "Quartus Prime Version 19.4.0 Build 64 12/04/2019 SC Pro Edition") fails to assign drivers to some of the ...
JKuba2's avatar
JKuba2
Icon for New Contributor rankNew Contributor
5 years ago

Hello

Well, this workaround fixes the non-working short aggregate assignment by not using the short aggregate assignment. I know how to do that, too. The point was to be able to assign multiple signals from one signal without having to explicitly write the width of each and every one of them and thus shorten the code and make it more clear and readable. I know I can make it work the same way without the aggregates. But it bugs me that it doesn't work in this specific case, even though it should.

I'm glad to see that someone was actually assigned to look into this, but this is not the result I was looking for, sadly. What I'm looking for is at least a hint suggesting that someone will try to fix the bug in the synthesis tool, even if it is in a version a year from now.

Thanks.

Best regards,

JKuba2