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JKuba2's avatar
JKuba2
Icon for New Contributor rankNew Contributor
6 years ago

BUG REPORT: VHDL 2008 target aggregate assignment leads to missing driver Warning

Hello, I'm using target aggregates in VHDL 2008 and I found out, that Quartus (specifically "Quartus Prime Version 19.4.0 Build 64 12/04/2019 SC Pro Edition") fails to assign drivers to some of the ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

For 1-bit signal, you have to use std_logic instead of std_logic_vector.

Thanks.

Best regards,

KhaiY