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Altera_Forum's avatar
Altera_Forum
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11 years ago

Avalon BFM - Test Program

Hi,

I just succesfully generated my first Avalon BFM testbench with Qsys 14. I have a component that consist of my avalon entity and an additional library file that contains some system wide constants.

The Qsys "generate" procedure generated a big file structure with a testbenchfile that I suppose to use in some kind of "test program" that uses the BFM API described in the document "Introduction to Avalon Verification IP Suite".

I'm currently stuck where I have to set up a little tcl script that compiles my testbench design in modelsim. The script looks like this and is based on the BFM example found here: http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html (http://www.altera.com/support/examples/design-flow/exm-avalon-verification-ip.html) 


#  setup variables for simulation script
set system_name      ads1158_bfm_test_tb
set QSYS_SIMDIR      $system_name/simulation
set TOP_LEVEL_NAME   tb
source $QSYS_SIMDIR/mentor/msim_setup.tcl
#  compile system
dev_com
com
#  compile testbench and test program
# vcom test_program_pkg.vhd
# vcom test_program.vhd
# vcom tb.vhd
#  load and run simulation
# elab_debug
# do wave.do
# run 50ns
#  alias to re-compile changes made to test program, load and run simulation
# alias rerun {
#    vcom test_program_pkg.vhd
#    vcom test_program.vhd
#    elab_debug
#    do wave.do
#    run 50ns
# }

If I call this in modelsim, the output is as follows: 


do run_ads_1158_bfm_simulation.tcl
#  ads1158_bfm_test_tb
#  ads1158_bfm_test_tb/simulation
#  tb
#   file_copy 
#  List Of Command Line Aliases 
#  
#  file_copy                     -- Copy ROM/RAM files to simulation directory 
#  
#  dev_com                       -- Compile device library files 
#  
#  com                           -- Compile the design files in correct order 
#  
#  elab                          -- Elaborate top level design 
#  
#  elab_debug                    -- Elaborate the top level design with novopt option 
#  
#  ld                            -- Compile all the design files and elaborate the top level design 
#  
#  ld_debug                      -- Compile all the design files and elaborate the top level design with -novopt 
#  
#  
#  
#  List Of Variables 
#  
#  TOP_LEVEL_NAME                -- Top level module name. 
#  
#  SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module. 
#  
#  QSYS_SIMDIR                   -- Qsys base simulation directory. 
#  
#  QUARTUS_INSTALL_DIR           -- Quartus installation directory. 
#   dev_com 
#   com 
#  Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013
#  
#  Top level modules:
#  	--none--
#  Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013
#  
#  Top level modules:
#  	--none--
#  Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013
#  
#  Top level modules:
#  	--none--
#  Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013
#  
#  Top level modules:
#  Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013
#  
#  Top level modules:
#  Model Technology ModelSim ALTERA vcom 10.1e Compiler 2013.06 Jun 12 2013
#  -- Loading package STANDARD
#  -- Loading package TEXTIO
#  -- Loading package std_logic_1164
#  -- Loading package NUMERIC_STD
#  ** Error: (vcom-11) Could not find work.rts_data_transfer.
#  ** Error: ads1158_bfm_test_tb/simulation/submodules/ads1158_interface.vhd(39): (vcom-1195) Cannot find expanded name "work.rts_data_transfer".
#  ** Error: ads1158_bfm_test_tb/simulation/submodules/ads1158_interface.vhd(39): Unknown expanded name.
#  ** Error: ads1158_bfm_test_tb/simulation/submodules/ads1158_interface.vhd(41): VHDL Compiler exiting
#  ** Error: /opt/altera/14.0/modelsim_ase/linux/vcom failed.
#  Error in macro ./run_ads_1158_bfm_simulation.tcl line 9
#  /opt/altera/14.0/modelsim_ase/linux/vcom failed.
#      while executing
#  "vcom     "$QSYS_SIMDIR/submodules/ads1158_interface.vhd"                                                           -work ads1158_interface_0          ..."
#      ("eval" body line 8)
#      invoked from within
#  "com"

I really don't know, where I should point the modelsim software to into the filestructure that Qsys created by generating my BFM testbench.

I guess that modelsim complains that it does not find my little library file (that contains my systemwide constants). I don't know, how I can fix this issue and honestly, I don't know how to proceed from there if it is fixed.

I know from the examples that I need an additional program file that actualle calls the BFM API, but i don't know how to implement a small program that e.g. starts the clock of my testbench ticking.

Can somebody provide a little guidance on that? And of course a solution for the above shown modelsim error?

Thank you!

Maik

14 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    One last question before I start using those BFMs of yours: I asume that it is possible to implement an avalon busstructure, where I provide the aforementinoed avalon master and two avalon slave (the data source and the data sink) components and connect those with your BFMs, right. This data transfer between my avalon master and slave components is something I have to heavy test because in there I somwhere have a bad bug that is annoying to search in the real system with signal tap.

    --- Quote End ---

    Create a Qsys system, so that you know you are testing Altera's Avalon-MM fabric;

    1. Add your Avalon-MM slaves

    2. Export an Avalon-MM master interface (I forget how to do this, but I'm pretty sure there is an option in the Qsys GUI now, previously I just created a basic _hw.tcl file)

    Save that and generate a VHDL simulation model. Your testbench can then;

    1. Instantiate the Qsys system

    2. Connect the BFM master to the exported master interface

    3. Connect the BFM server and testcase generator

    Model your code after: 

    
ESC-104Code_Hawkins\dsp_tutorial\vhdl\lib\altera_avalon\test\avalon_bfm_tb.vhd

    where the Avalon-MM slave register is replaced with your Qsys system, and the Avalon-MM signals from the BFM server connect to the master ports exported on the Qsys system.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi Maik,

    Sorry, I can't help you for a few days, as I'll be traveling. Ping me on Friday if you're still stuck.

    If your questions are related to the VHDL verification suite functions, file a Service Request with Altera and get some direct/official help.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi Dave,

    just for information: I filed a SR to Altera 3 days ago. No answer, yet . . . .

    At least, our discussion and your tutorial opened my mind for the fact that I can use the Qsys simulation model for the simulation of my custom master that is connected to 2 of my custom slave components. The model from Qsys contains all the interconnect, so that i was able to fix a lot of my problems until now.

    Since the master runs "free" without configuration, I just needed to put one of the slaves in simulation mode, which I did the old way by just writing some avalon transfers in my testbench file by hand.

    The same I did for the AXI read of the other slave . . . It is not nice, but it works for now.

    If I get an answer for my SR, i will post some results, here, too.

    Besides, I had a look at the VHDL-2008 additions and agree, that the hierarchical signal access looks quiet usable and it is a pitty that Altera has choosen the BFM ID approach for their verification API . . . .

    Regards,

    Maik
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi,

    I just wanted to post a little update here about my findings about BFMs + VHDL.

    I'm now able to play with the BFMs through VHDL. Basically what I do is:

    1. I create a system in QSys with my custom Avalon MM Slave components thati would like to test.

    2. I connect the slave interface to an instantiation of the Avalom MM Master BFM and configure it to my needs (bus withs, signal polarity, etc., etc.).

    3. I export all conduits and the clock and reset signals from all components.

    4. I let QSys generate the simulation model (in VHDL).

    5. I use the run_simulation.tcl script taken from the "Introduction to Avalon Verification IP Suite User Guide"-example for simulations in modelsim.

    5a. I adjust the variable "system_name" to my Qsys project name.

    5b. I removed the test_prgram_pkg.vhd file compilation from the script in order to get rid of all the definitions that i don't understand, yet.

    5c. I provide an own test_program.vhd file where I just (until now) set up a basic Avalon write transfer like this: 

    procedure avalon_write( address : in integer; data : in integer) is
  begin
    set_command_request(master_bfm.altera_avalon_mm_master_bfm_vhdl_pkg.REQ_WRITE, AVALON_MASTER_BFM_VHDL_ID, req_if);
    set_command_idle(0, 0, AVALON_MASTER_BFM_VHDL_ID, req_if);
    set_command_init_latency(0, AVALON_MASTER_BFM_VHDL_ID, req_if);
    set_command_address(address, AVALON_MASTER_BFM_VHDL_ID, req_if);    
    set_command_data(data, 0, AVALON_MASTER_BFM_VHDL_ID, req_if);
    push_command(0, req_if);
  end procedure avalon_write;

    I use this procedure in the test_program.vhd file to initiate Avalon writes at certain events or times.

    As one can see, I tried to base this on Daves Veriog examples, since I think that these are nicely structured.

    I have problems still on waiting for responses in order to be sure that the transfer is finished since I never get a value of "1" as pending responses so that I'm in an endless loop if I do so. This is why I left this out here. (I wonder how one can get a response to a write transfer anyway?!?).

    6. I provide a testbench tb.vhd file where I instatiate the Qsys system along with my test_program and where I generate clock and reset signals.

    7. I do a "source run_simulation.tcl" in modeslim and voilà, I have the defined communication on the Avalon bus without all the overhead of the Altera provided examples that I do not fully understand.

    As you can see, there are still questions left like why do I not get any response on my write transfer. Maybe somebody can answer this or I have to figure out myself ;-).

    Regards,

    Maik