Avalon BFM - Test Program

Hi Dave,

just for information: I filed a SR to Altera 3 days ago. No answer, yet . . . .

At least, our discussion and your tutorial opened my mind for the fact that I can use the Qsys simulation model for the simulation of my custom master that is connected to 2 of my custom slave components. The model from Qsys contains all the interconnect, so that i was able to fix a lot of my problems until now.

Since the master runs "free" without configuration, I just needed to put one of the slaves in simulation mode, which I did the old way by just writing some avalon transfers in my testbench file by hand.

The same I did for the AXI read of the other slave . . . It is not nice, but it works for now.

If I get an answer for my SR, i will post some results, here, too.

Besides, I had a look at the VHDL-2008 additions and agree, that the hierarchical signal access looks quiet usable and it is a pitty that Altera has choosen the BFM ID approach for their verification API . . . .

Regards,

Maik