Avalon BFM - Test Program

Hi,

I just wanted to post a little update here about my findings about BFMs + VHDL.

I'm now able to play with the BFMs through VHDL. Basically what I do is:

1. I create a system in QSys with my custom Avalon MM Slave components thati would like to test.

2. I connect the slave interface to an instantiation of the Avalom MM Master BFM and configure it to my needs (bus withs, signal polarity, etc., etc.).

3. I export all conduits and the clock and reset signals from all components.

4. I let QSys generate the simulation model (in VHDL).

5. I use the run_simulation.tcl script taken from the "Introduction to Avalon Verification IP Suite User Guide"-example for simulations in modelsim.

5a. I adjust the variable "system_name" to my Qsys project name.

5b. I removed the test_prgram_pkg.vhd file compilation from the script in order to get rid of all the definitions that i don't understand, yet.

5c. I provide an own test_program.vhd file where I just (until now) set up a basic Avalon write transfer like this:

procedure avalon_write( address : in integer; data : in integer) is
  begin
    set_command_request(master_bfm.altera_avalon_mm_master_bfm_vhdl_pkg.REQ_WRITE, AVALON_MASTER_BFM_VHDL_ID, req_if);
    set_command_idle(0, 0, AVALON_MASTER_BFM_VHDL_ID, req_if);
    set_command_init_latency(0, AVALON_MASTER_BFM_VHDL_ID, req_if);
    set_command_address(address, AVALON_MASTER_BFM_VHDL_ID, req_if);    
    set_command_data(data, 0, AVALON_MASTER_BFM_VHDL_ID, req_if);
    push_command(0, req_if);
  end procedure avalon_write;

I use this procedure in the test_program.vhd file to initiate Avalon writes at certain events or times.

As one can see, I tried to base this on Daves Veriog examples, since I think that these are nicely structured.

I have problems still on waiting for responses in order to be sure that the transfer is finished since I never get a value of "1" as pending responses so that I'm in an endless loop if I do so. This is why I left this out here. (I wonder how one can get a response to a write transfer anyway?!?).

6. I provide a testbench tb.vhd file where I instatiate the Qsys system along with my test_program and where I generate clock and reset signals.

7. I do a "source run_simulation.tcl" in modeslim and voilà, I have the defined communication on the Avalon bus without all the overhead of the Altera provided examples that I do not fully understand.

As you can see, there are still questions left like why do I not get any response on my write transfer. Maybe somebody can answer this or I have to figure out myself ;-).

Regards,

Maik