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One last question before I start using those BFMs of yours: I asume that it is possible to implement an avalon busstructure, where I provide the aforementinoed avalon master and two avalon slave (the data source and the data sink) components and connect those with your BFMs, right. This data transfer between my avalon master and slave components is something I have to heavy test because in there I somwhere have a bad bug that is annoying to search in the real system with signal tap.
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Create a Qsys system, so that you know you are testing Altera's Avalon-MM fabric;
1. Add your Avalon-MM slaves
2. Export an Avalon-MM master interface (I forget how to do this, but I'm pretty sure there is an option in the Qsys GUI now, previously I just created a basic _hw.tcl file)
Save that and generate a VHDL simulation model. Your testbench can then;
1. Instantiate the Qsys system
2. Connect the BFM master to the exported master interface
3. Connect the BFM server and testcase generator
Model your code after:
ESC-104Code_Hawkins\dsp_tutorial\vhdl\lib\altera_avalon\test\avalon_bfm_tb.vhd
where the Avalon-MM slave register is replaced with your Qsys system, and the Avalon-MM signals from the BFM server connect to the master ports exported on the Qsys system.
Cheers,
Dave
Honored Contributor
