Automatic VHDL Code Generation Programmatically

Question

We are actually working on a Double Precision IIR filter. We are interested in making a very generic filter which could support variety of functionalities. For some reason, VHDL generics are not superior enough to support this task. We are thinking of adopting an approach where we can generate required VHDL code programmatically:

Following are few requirements we have for this tool

- allows plugging in already present VHDL entities

- allow manipulation of existing VHDL

- create customized VHDL code inside VHDL template with entity, architectures etc.

- Additionally support test bench generation

- Provide memory interfacing

- Allow easy future upgrades in IP

- Focus on DSP circuits

- Optionally allow to verify design

Megawizard in Quartus seems to be using some in-built EDA API to generate custom HDL code. Any idea what sort of libraries or framework Altera uses for VHDL code generation in megawizard?

Besides, I have come across two free tools: vMagic and MyHDL. I am still exploring them.

If you know any other superior tool(open-source) for automatic VHDL code generation manipulation, that would be really nice

Thanks

Varun

altera_forum · Answer

The problem is, FPGA designs tend to get quite tight with resources. generated code often produces designs that use a lot more resources than would be the case with something that was hand coded. So you can see the friction here.

Mathwoks offer HDL coder that generates generic HDL from simulink designs, but its a bit limited in what it can do. But it can all the things you're asking for.

altera_forum · Answer

I think understand what you are trying to say. Actually I am not looking for High Level Synthesis tool or model based synthesis toolflow.

I still want to work at RTL level but instead of handcoding VHDL I am interesting in using some library (Java,Python etc.) in which I could programmatic-ally generate HDL.

altera_forum · Answer

I have seen VHDL generated from Python before, but have not done it myself. At the time, the python just connected together a load of pre-written blocks.

altera_forum · Answer

you should take a look at DSP Builder Advanced Blockset  i've used Python (not myHDL) to generate VHDL. i used it mostly as a time saver, not to increase flexibility

altera_forum · Answer

I have used Python extensively for VHDL code generation. In addition, I have described a set of routines that make up a small declarative language. The Mako templating engine is excellent; it is the main tool used for automatic generation of entity, architecture, and configurable parameters that in VHDL are made as constants.

On top of this, the Qt GUI toolkit makes it easy to build applications with Python. I formerly used PyQt, but now Nokia has ported Qt to Python in the form of the module PySide, which has a freer license that PyQt.

James

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Automatic VHDL Code Generation Programmatically

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