Auto gated clock convert to clock enable

I get a ASIC design which want to be verified on FPGA.

I know Quartus support "Auto gated clock convert to clock enable" recently.

Web: https://www.intel.com/content/www/us/en/programmable/quartushelp/15.1/index.htm#verify/da/comp_file_rules_clock.htm?elq_cid=7936472_ts1634786187118&erpm_id=10817332_ts1634786187118

From the above web, I know that case(1) can completely support gated clock conversion.

How about case(2)? Can latch-based clock gating work for gated clock conversion?

Should I do formal verification when "Auto gated clock convert to clock enable" is turned on.

How about case(3)?

Case(1): Note that enable_a is from the clock_a domain.

assign gated_clock_a=clock_a & enable_a;

assign gated_clock_a=clock_a | enable_a;

Case(2): Latch-based clock gating

always@(*) begin

if (~clock_a )

enable_a <= enable;

end

assign gated_clock_a= clock_a & enable_a ;

Case(3): Note that enable_a is from the clock_a domain.

Note that enable_a2 is from the gated_clock_a domain.

assign gated_clock_a = clock_a & enable_a;

assign gated_clock_a2 = gated_clock_a | enable_a2;

Thank you very much.