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NuvKFC's avatar
NuvKFC
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4 years ago
Solved

Auto gated clock convert to clock enable

I get a ASIC design which want to be verified on FPGA. I know Quartus support "Auto gated clock convert to clock enable" recently. Web: https://www.intel.com/content/www/us/en/programmable/quart...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


It depends on your device. It's supported in Arria® series, Cyclone® II, Cyclone III, Cyclone IV, Stratix® II, Stratix II GX, Stratix III, Stratix IV, and Stratix V devices.


You can refer to section 2.2.3.5 here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-design-recommendations-19-1.pdf#page=65


And this help page; https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops/def_synth_gated_clock_conversion.htm


Regards,

Nurina


  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

    Regards,
    Nurina

    P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!

    • NuvKFC's avatar
      NuvKFC
      Icon for Contributor rankContributor
      4 years ago

      Hi NurinaW

      OK. Thank you, NurinaW, very much.