NuvKFC
Contributor
4 years agoAuto gated clock convert to clock enable
I get a ASIC design which want to be verified on FPGA.
I know Quartus support "Auto gated clock convert to clock enable" recently.
Web: https://www.intel.com/content/www/us/en/programmable/quart...
- 4 years ago
Hi,
Sorry for the late response. From what I know, case 2 is allowed.
You can refer to pages 12-10 to 12-12 of this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii51006.pdf#page=10
Is case 3 a cascaded clock gating? This only works on certain devices, I think it's best you don't use this method since you're doing ASIC prototyping.
Regards,
Nurina