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Altera_Forum's avatar
Altera_Forum
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11 years ago

Async FIFO 2 Clock code advice - VHDL

Hi all,

I want to ask if someone can advice me an Async FIFO with 2 clocks code in VHDL that works. I know Xilinx provide already build in FIFO IP core, but since I want possibility to migrate my code also to other devices I need a code that I can easy port.

Thank you.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Altera have a DC fifo megafunction. You can generate one with the Megawizard/ipcatalogue or manually instatiate one yourself (if you are familiar with using the altera_mf_components library and reading the documentation).

    If you need code that is compilable on both altera and Xilinx, you have 2 options:

    1. Make a wrapper around the dc fifo/xilinx fifo that uses a generic to differentiate the manufacturere)

    2. Write your own DC fifo (you need to be really careful how you cross the clock domains).

    The first option may be the easiest.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thanks for you answer. But I need the possibilty to use this code also with devices not from Xilinx or Altera. The second option have a problem that I can't really know if my code will be without errors or optimized. So I ask if someone have an opensource Async FIFO.