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Altera_Forum's avatar
Altera_Forum
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10 years ago

Async FIFO 2 Clock code advice - VHDL

Hi all, I want to ask if someone can advice me an Async FIFO with 2 clocks code in VHDL that works. I know Xilinx provide already build in FIFO IP core, but since I want possibility to mig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thanks for you answer. But I need the possibilty to use this code also with devices not from Xilinx or Altera. The second option have a problem that I can't really know if my code will be without errors or optimized. So I ask if someone have an opensource Async FIFO.