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Altera_Forum
Honored Contributor
Honored ContributorAsync FIFO 2 Clock code advice - VHDL
Hi all, I want to ask if someone can advice me an Async FIFO with 2 clocks code in VHDL that works. I know Xilinx provide already build in FIFO IP core, but since I want possibility to mig...
Altera_ForumHonored Contributor
Honored ContributorAltera have a DC fifo megafunction. You can generate one with the Megawizard/ipcatalogue or manually instatiate one yourself (if you are familiar with using the altera_mf_components library and reading the documentation).
If you need code that is compilable on both altera and Xilinx, you have 2 options: 1. Make a wrapper around the dc fifo/xilinx fifo that uses a generic to differentiate the manufacturere) 2. Write your own DC fifo (you need to be really careful how you cross the clock domains). The first option may be the easiest.
