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MMavi's avatar
MMavi
Icon for New Contributor rankNew Contributor
7 years ago

Assembler does not generate programming files when it run in the compilation flow

Hi,

I have a project that assembler does not generate programming files when it runs in the compilation flow and gives a warning that says "Can't generate programming files for the project because the encrypted source file cannot be located: "sdi_*.v"". The files it listed are added to the project(via .qip file)(it is a SDI v17.1 IP). If I run Assembler individually, it generates the programming files without problem and with no warning. I can make progress in my project but I have to run assembler again after every compilation.

I use Quartus Prime 17.1

How can I solve this ? I couldn't find any solution online yet.

8 Replies

    • MMavi's avatar
      MMavi
      Icon for New Contributor rankNew Contributor
      7 years ago
      Hi, Sorry, i forgot about this. It's been busy at work since. I still have the problem. I tried creating a new project but it didnt work either. If there is a work around or fix you can recommend. I can try them out. Thanks, Mehdi Sent from my Samsung Galaxy smartphone.
  • JoanneSinY_L_Intel's avatar
    JoanneSinY_L_Intel
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    ​Hi,

    Can you try

    Go to Assignments -> Settings

    Compilation Process settings

    Make sure "Run Assembler during compilation" is ticked.

    Thanks

    joanne

    • MMavi's avatar
      MMavi
      Icon for New Contributor rankNew Contributor
      7 years ago
      Yes it is checked. Sent from my Samsung Galaxy smartphone.
    • JoanneSinY_L_Intel's avatar
      JoanneSinY_L_Intel
      Icon for Occasional Contributor rankOccasional Contributor
      7 years ago

      Hi,

      I am able to solve the warning and generate out the programming file by specify the verilog path for the file in QSF file

      set_global_assignment -name VERILOG_FILE ipcores/gxb_txsample_2xhd.v

      set_global_assignment -name VERILOG_FILE ipcores/hdsdi_insert_ln.v

      set_global_assignment -name VERILOG_FILE ipcores/sdi_clocks.v

      set_global_assignment -name VERILOG_FILE ipcores/sdi_scrambler.v

      set_global_assignment -name VERILOG_FILE ipcores/fifo_4x20.v

      set_global_assignment -name VERILOG_FILE ipcores/sdi_trsmatch.v

      set_global_assignment -name VERILOG_FILE ipcores/sdi_megacore_top.v

      set_global_assignment -name VERILOG_FILE ipcores/sdi_tr_gxb_interface.v

      set_global_assignment -name VERILOG_FILE ipcores/hdsdi_crc.v

      Could you try and see and tell me the outcomes?

      Regards

      Joanne

      • MMavi's avatar
        MMavi
        Icon for New Contributor rankNew Contributor
        7 years ago

        Hi,

        It worked. Also I specify the paths in .qip file of the SDI IP to not overcrowd the files tab.

        Thank you.

        Regards,

        Mehdi