Forum Discussion
Hi,
I am able to solve the warning and generate out the programming file by specify the verilog path for the file in QSF file
set_global_assignment -name VERILOG_FILE ipcores/gxb_txsample_2xhd.v
set_global_assignment -name VERILOG_FILE ipcores/hdsdi_insert_ln.v
set_global_assignment -name VERILOG_FILE ipcores/sdi_clocks.v
set_global_assignment -name VERILOG_FILE ipcores/sdi_scrambler.v
set_global_assignment -name VERILOG_FILE ipcores/fifo_4x20.v
set_global_assignment -name VERILOG_FILE ipcores/sdi_trsmatch.v
set_global_assignment -name VERILOG_FILE ipcores/sdi_megacore_top.v
set_global_assignment -name VERILOG_FILE ipcores/sdi_tr_gxb_interface.v
set_global_assignment -name VERILOG_FILE ipcores/hdsdi_crc.v
Could you try and see and tell me the outcomes?
Regards
Joanne
Hi,
It worked. Also I specify the paths in .qip file of the SDI IP to not overcrowd the files tab.
Thank you.
Regards,
Mehdi