arithmetic mode for LE from vhdl

Question

I have searched many threads for the solution and the answers were incomplete. So i try to do some investigation. this code in vhdl definitely put your counter in arithmetic mode for LE. if you have any suggestion please share it with me. process(reset, clk, count_en)
        variable v : unsigned(cnt_reg'length downto 0);
    begin
        if reset = '1' then
            cnt_reg &lt;= (others =&gt; '0');
            cnt_full &lt;= '0'; -- it means counter foolish your 
        elsif rising_edge(clk) then
            if count_en = '1' then
                v := ('0' &amp; cnt_reg) + (to_unsigned(0,v'length-1) &amp; count_en); -- if you add with constant you cannot get arithmetic mode for LE
                cnt_reg &lt;= v(v'high-1 downto 0);
                cnt_full &lt;= v(v'high);
            end if;
        end if;
    end process;

altera_forum · Answer

it seems that the very first LE do not use carry-in but it may . So the quetion is how to put a 'one' on the very first LE to cin input.

ps : the last element in counter (at msb) could run in arithmetic mode, but you should read the overflow counter value otherwise it run in normal mode.

altera_forum · Answer

It can only use the cin if count-en is generated on a LE in the same LE column so that it can put the signal on the carry chain, which I assume it isn't.

Why do you use count en as the add word? This will just get converted to logic 1 because the register only enables the the input when enable is 1, hence you always add 1.

altera_forum · Answer

Tricky, you are right. But I was gleeful about the code above. Even if it is ugly and count only by one. I'l try my best )

altera_forum · Answer

--- Quote Start ---  It can only use the cin if count-en is generated on a LE in the same LE column so that it can put the signal on the carry chain, which I assume it isn't. Why do you use count en as the add word? This will just get converted to logic 1 because the register only enables the the input when enable is 1, hence you always add 1.  --- Quote End ---    okay. LE cin input accessable only by another LE. if i am wrong correct me. I don't know why quartus doesn't aware construction like cnt &lt;= cnt +1  as signal to itself for turning on arithmetic mode at synthesis. So it was a tricky with code so quartus able to turn on arithmetic mode automatically. btw, any arithmetic operations with constant don't turn on arithmetic mode. process(reset, clk, count_en)
        variable v : unsigned(cnt_reg'length downto 0);
    begin
        if reset = '1' then
            cnt_reg &lt;= (others =&gt; '0');
            cnt_full &lt;= '0';
        elsif rising_edge(clk) then
            if count_en = '1' then
                v := resize(cnt_reg, v'length) + (to_unsigned(0, cnt_reg'length) &amp; count_en);
                cnt_reg &lt;= resize(v, cnt_reg'length);
                cnt_full &lt;= v(v'high);
            end if;
        end if;
end process;

altera_forum · Answer

Can I try and understand why you are doing this?

A constant is "free" when it comes to timing. Using an input like about would just increase the amount of routing required, so technically slower and use more resources.

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arithmetic mode for LE from vhdl

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