arithmetic mode for LE from vhdl

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It can only use the cin if count-en is generated on a LE in the same LE column so that it can put the signal on the carry chain, which I assume it isn't.

Why do you use count en as the add word? This will just get converted to logic 1 because the register only enables the the input when enable is 1, hence you always add 1.

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okay. LE cin input accessable only by another LE. if i am wrong correct me.

I don't know why quartus doesn't aware construction like cnt <= cnt +1 as signal to itself for turning on arithmetic mode at synthesis. So it was a tricky with code so quartus able to turn on arithmetic mode automatically. btw, any arithmetic operations with constant don't turn on arithmetic mode.

process(reset, clk, count_en)
        variable v : unsigned(cnt_reg'length downto 0);
    begin
        if reset = '1' then
            cnt_reg <= (others => '0');
            cnt_full <= '0';
        elsif rising_edge(clk) then
            if count_en = '1' then
                v := resize(cnt_reg, v'length) + (to_unsigned(0, cnt_reg'length) & count_en);
                cnt_reg <= resize(v, cnt_reg'length);
                cnt_full <= v(v'high);
            end if;
        end if;
end process;