Agilex 7 F-tile PCIe questa simulation failed
Hello,
I followed ug20332 to generate F-tile PCIe example design and Questa simulation environment but get below error message, does any expert know the issue?
Best regards
** Note: (vsim-3812) Design is being optimized...
# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
# ** Error: ../../../../ip/pcie_ed/pcie_ed_syspll_inst/systemclk_f_300/sim/pcie_ed_syspll_inst_systemclk_f_300_p45yqwy.sv(1432): Module 'ctfb_avmm1_soft_logic' is not defined.
# For instance 'avmm1_ena_inst' at path 'pcie_ed_tb.pcie_ed.syspll_inst.syspll_inst.x_sip'
# ** Error: ../../../../pcie_ed_rp/ip/pcie_top/syspll/systemclk_f_300/sim/syspll_systemclk_f_300_p45yqwy.sv(1432): Module 'ctfb_avmm1_soft_logic' is not defined.
# For instance 'avmm1_ena_inst' at path 'pcie_ed_tb.dut_pcie_tb_ip.dut_pcie_tb.g_bfm.p_dut_ep.altpcietb_bfm_top_rp.g_bfm.u1.rp.inst.dut.syspll_inst.systemclk_f_inst.x_sip'
# Optimization failed
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=2, Warnings=1.
# Error loading design
# End time: 16:40:36 on Apr 25,2024, Elapsed time: 0:01:58
# Errors: 2, Warnings: 1, Suppressed Errors: 2