Accessing SDRAM Controller in Platform Designer from Verilog module through Avalon-MM interface

Greetings there, I am currently working on an image processing project using the DE1-SoC FPGA and is totally new to this.

My current project framework consisting of

1. A customized Verilog submodule that basically receives and writes out an N-bit pixel data to memory (which I hope is SDRAM) every clock edge.
2. A Platform Designer system, mainly connecting the Nios II processor with the SDRAM Controller IP and an Avalon-MM interface (the Avalon MM Master Translator IP).

3. I have connected 1 & 2 in a Verilog top-level module through module instantiation. In order to establish the data streaming between custom module in part 1 and SDRAM controller in part 2, I have connected the SDRAM controller as the Avalon-MM slave and exported the Avalon-MM master port to be connected to my customized module. In the module, I have designed an FSM to manage the read, process and write to the Avalon interface.

I can read and write data into the SDRAM using C code in the Nios II Eclipse. However, the FSM is not working, and what I found out is that the waitrequest from the SDRAM is always HIGH, which indicates that the SDRAM might not be ready for transaction. My main problem now is that I cannot access the SDRAM from Quartus Verilog module.

Is here anyone who have experience in using DE1-SoC SDRAM and Avalon interface? I have attached a screenshot for my system design in Platform Designer, my top-level (qsys_lab.v) and sub-level (HistogramEqualization_MM.v) Verilog module, including the Avalon-MM FSM, and the state diagram of the FSM. I really appreciate for all the help, thank you!System Design in Platform DesignerRTL netlist viewerFSM State Machine