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Star_night2001's avatar
Star_night2001
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1 year ago

Accessing SDRAM Controller in Platform Designer from Verilog module through Avalon-MM interface

Greetings there, I am currently working on an image processing project using the DE1-SoC FPGA and is totally new to this. My current project framework consisting of 1. A customized Verilog submodul...
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RichardT_altera's avatar
RichardT_altera
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1 year ago

This design look very familiar with the design from Terasic. Is your design from Terasic?

Terasic User Guide: https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=234&No=1021&PartNo=4#contents

You may refer to the example design and cross check with your design. (Note that you need Quartus Lite Edition to open the .par design file)

https://www.intel.com/content/www/us/en/design-example/715013/intel-max-10-fpga-sdram-rtl-design-example-terasic-de10-lite-board.html

You may contact Terasic Support for further support or modification.

Regards,

Richard Tan