New ContributorAfter adding the Verilog HDL File (named "sam") and creating the program
When I compile
The following error appears.
“top-level design entity “sam” is undefined”
Settings → General "top-level entity" is "sam".
Even if I right-click "sam.V" in "Project Navigator" and select "Set as top-level entity" and compile, the same error occurs.
I would like to know how to solve this problem.
ContributorInside your file sam.v, is there actually a definition for a module called sam?
New Contributorファイル sam.v 内というのがどの場所を示すのかわかっていないのですが、
プロジェクト及びプログラムの保存先は添付の画像通りの内容になります。
モジュールの定義があるか確認はどこを見れば良いでしょうか。
詳しく教えていただけると助かります。
以上、よろしくお願いいたします。
ContributorNavigate to the file sam.v. Open the file in a text editor. What is the content of the file? Please post it here.
Super ContributorHe meant that the module name must match the file name. Please refer to the picture below for clarification.
Regards,
Richard Tan
Super ContributorI believe your inquiries are answered.
Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.
Thank you and have a great day!
Best Regards,
Richard Tan
