Forum Discussion
Ryo10
New Contributor
2 years agoAbout Quartus Prime
After adding the Verilog HDL File (named "sam") and creating the program When I compile The following error appears. “top-level design entity “sam” is undefined” Settings → General "top-level ent...
RichardT_altera
Super Contributor
2 years agoI believe your inquiries are answered.
Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.
Thank you and have a great day!
Best Regards,
Richard Tan