Forum Discussion
Ryo10
New Contributor
New ContributorAbout Quartus Prime
After adding the Verilog HDL File (named "sam") and creating the program When I compile The following error appears. “top-level design entity “sam” is undefined” Settings → General "top-level ent...
RichardT_altera
Super Contributor
Super ContributorHe meant that the module name must match the file name. Please refer to the picture below for clarification.
Regards,
Richard Tan
