Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

A very new FPGA developer is very stuck. I think I have timing issues

Hi!

I am working on my first FPGA project ever. I have an Altera DE2 board and was following their "Quartus II introduction using verilog design" document.

Got through the tutorial with no issues(skipped simulation... probably my later issue)

Now, my first step for my learning is to make 4 leds light up and move across the red led array on the board.

here is the code in verilog(my first attempt so probably not that good) 


module binaryShift(
	// this is the 27MHZ  onboard clock 
	input CLOCK_27,
	//push buttons
	input  KEY,
	//dpdt switches
	input  SW,
	//7-SEG Displays
	output  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
	//LEDs
	output    LEDG,  //  LED Green
	output    LEDR,  //  LED Red
	//GPIO CONNECTIONS
	inout    GPIO_0, GPIO_1
);
// Blank the unused HEX displays
assign HEX7 = 7'h7f;
assign HEX6 = 7'h7f;
assign HEX5 = 7'h7f;
assign HEX4 = 7'h7f;
assign HEX3 = 7'h7f;
assign HEX2 = 7'h7f;
assign HEX1 = 7'h7f;
assign HEX0 = 7'h7f;
//assign LEDR = 18'h12;
reg paddle;
always @(negedge KEY or negedge KEY)
begin
if(!KEY)
begin
case(paddle)
			18'b000000000000001111 : paddle <= 18'b111100000000000000;
			18'b000000000000011110 : paddle <= 18'b000000000000001111;
			18'b000000000000111100 : paddle <= 18'b000000000000011110;
			18'b000000000001111000 : paddle <= 18'b000000000000111100;
			18'b000000000011110000 : paddle <= 18'b000000000001111000;
			18'b000000000111100000 : paddle <= 18'b000000000011110000;
			18'b000000001111000000 : paddle <= 18'b000000000111100000;
			18'b000000011110000000 : paddle <= 18'b000000001111000000;
			18'b000000111100000000 : paddle <= 18'b000000011110000000;
			18'b000001111000000000 : paddle <= 18'b000000111100000000;
			18'b000011110000000000 : paddle <= 18'b000001111000000000;
			18'b000111100000000000 : paddle <= 18'b000011110000000000;
			18'b001111000000000000 : paddle <= 18'b000111100000000000;
			18'b011110000000000000 : paddle <= 18'b001111000000000000;
			18'b111100000000000000 : paddle <= 18'b011110000000000000;
			default: paddle <= 18'b111100000000000000;
		endcase
end
else begin
	paddle <= ~paddle;
end
end
assign LEDR = paddle;
endmodule

the code seems pretty straight forward, but what happens is when I press the button the leds do follow the shifting pattern sort of, but after a press or 2 I get odd patterns not in the case statements... things like 10110111000000000....

My guess is that this is an issue in the timing because I get a lot of warnings about it. The problem now is I have 10.1 web edition which no longer has the vector waveform files like the tutorial shows. I have read through the forums that this question has been asked but only found people telling that the solution does exist and go find it. I know modelsim is the partial solution to doing the timing simulation but have not been able to figure out how to go from quartus to modelsim and back to the board. Has altera put out a tutorial for the newer version of quartus?

any help would be fantastic and greatly appreciated.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    try initialise paddle to some known value.

    --- Quote End ---

    Tried, added: 

    
initial
begin
paddle <= 18'b111100000000000000;
end

    No change, I have a ton of warnings(1123) with 2 critical warnings, both of which are "Timing requirements not met"
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You should register the paddle on the clock edge, not on any other signal.

    27MHz shouldn't be a problem for your code. Do you have timing constraints (sdc file)?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    you are not using the clock.

    No clock means no timing to analyse on registers and hence no violations of tSU/tH expected !!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I do not have a timing constraints file, How do I generate one? is that done in modelsim?

    when you say register the paddle on the clock edge do you mean, somethign like

    always @ (negedge KEY[2] and posedge clock)

    I'm a little unsure of the right way to set up a clock... time to do some online hunting
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    always @(negedge clock_27)

    try first without sdc then you can find a template at timequest resource centre (altera website)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Works perfectly :). here is the modified code if snyone else has this issue: 

    
module binaryShift(
	// this is the 50MHZ  onboard clock 
	input CLOCK_27,
	//push buttons
	input  KEY,
	//dpdt switches
	input  SW,
	//7-SEG Displays
	output  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
	//LEDs
	output    LEDG,  //  LED Green
	output    LEDR,  //  LED Red
	//GPIO CONNECTIONS
	inout    GPIO_0, GPIO_1
);
// Blank the unused HEX displays
assign HEX7 = 7'h7f;
assign HEX6 = 7'h7f;
assign HEX5 = 7'h7f;
assign HEX4 = 7'h7f;
assign HEX3 = 7'h7f;
assign HEX2 = 7'h7f;
assign HEX1 = 7'h7f;
assign HEX0 = 7'h7f;
//assign LEDR = 18'h12;
reg paddle;
reg pressed;
initial
	begin
	paddle <= 18'b111100000000000000;
	pressed <= 1'b0;
	end
always @( negedge CLOCK_27)
	begin
	if (KEY)
	begin 
		pressed <= 1'b0;
	end
	if(!KEY && !pressed)
	begin
		pressed <= 1'b1;
		case(paddle)
					18'b000000000000001111 : paddle <= 18'b111100000000000000;
					18'b000000000000011110 : paddle <= 18'b000000000000001111;
					18'b000000000000111100 : paddle <= 18'b000000000000011110;
					18'b000000000001111000 : paddle <= 18'b000000000000111100;
					18'b000000000011110000 : paddle <= 18'b000000000001111000;
					18'b000000000111100000 : paddle <= 18'b000000000011110000;
					18'b000000001111000000 : paddle <= 18'b000000000111100000;
					18'b000000011110000000 : paddle <= 18'b000000001111000000;
					18'b000000111100000000 : paddle <= 18'b000000011110000000;
					18'b000001111000000000 : paddle <= 18'b000000111100000000;
					18'b000011110000000000 : paddle <= 18'b000001111000000000;
					18'b000111100000000000 : paddle <= 18'b000011110000000000;
					18'b001111000000000000 : paddle <= 18'b000111100000000000;
					18'b011110000000000000 : paddle <= 18'b001111000000000000;
					18'b111100000000000000 : paddle <= 18'b011110000000000000;
					default: paddle <= 18'b111100000000000000;
				endcase
	end
	else if (!KEY) begin
		paddle <= ~paddle;
	end
end
assign LEDR = paddle;
endmodule

    now, So I added the "pressed" register so that it didn't keep cycling the case statements while the button was pressed, is there a better way to do this code?

    Like I said , I am still very much learning and any critique of my code will be very much appreciated.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    That is very good for a beginner.

    The issue was timing but due to logic hazards of asynchronous design.

    Asynchronous design can be very very fast but needs exceptional skills to master it against hazards. Using the clock as sampling signal, decision are done on the edge when logic levels have settled... fpgas are meant for clocked design (RTL)