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Altera_Forum
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14 years ago

A very new FPGA developer is very stuck. I think I have timing issues

Hi! I am working on my first FPGA project ever. I have an Altera DE2 board and was following their "Quartus II introduction using verilog design" document. Got through the tutorial with no...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

That is very good for a beginner.

The issue was timing but due to logic hazards of asynchronous design.

Asynchronous design can be very very fast but needs exceptional skills to master it against hazards. Using the clock as sampling signal, decision are done on the edge when logic levels have settled... fpgas are meant for clocked design (RTL)