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Altera_Forum
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14 years ago

A very new FPGA developer is very stuck. I think I have timing issues

Hi! I am working on my first FPGA project ever. I have an Altera DE2 board and was following their "Quartus II introduction using verilog design" document. Got through the tutorial with no...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You should register the paddle on the clock edge, not on any other signal.

27MHz shouldn't be a problem for your code. Do you have timing constraints (sdc file)?