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Altera_Forum
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14 years ago

A very new FPGA developer is very stuck. I think I have timing issues

Hi! I am working on my first FPGA project ever. I have an Altera DE2 board and was following their "Quartus II introduction using verilog design" document. Got through the tutorial with no...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I do not have a timing constraints file, How do I generate one? is that done in modelsim?

when you say register the paddle on the clock edge do you mean, somethign like

always @ (negedge KEY[2] and posedge clock)

I'm a little unsure of the right way to set up a clock... time to do some online hunting