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Altera_Forum
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14 years ago

A very new FPGA developer is very stuck. I think I have timing issues

Hi! I am working on my first FPGA project ever. I have an Altera DE2 board and was following their "Quartus II introduction using verilog design" document. Got through the tutorial with no...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

--- Quote Start ---

try initialise paddle to some known value.

--- Quote End ---

Tried, added: 


initial
begin
paddle <= 18'b111100000000000000;
end

No change, I have a ton of warnings(1123) with 2 critical warnings, both of which are "Timing requirements not met"