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Altera_Forum
Honored Contributor
Honored Contributor7segments verilog erorrs
hi, I'm trying to create a verilog file for 2 digit 7 segments, I've created the truth table and derive the equation using kmap
but I faced a errors when analyse&synthesis :( the code is :module operation3 (a2, a1, a0, b2, b1, A1, B1, C1, D1, E1, F1, G1, A2, B2, C2, D2, E2, F2, G2);
input a2, a1, a0, b2, b1;
output A1, B1, C1, D1, E1, F1, G1, A2, B2, C2, D2, E2, F2, G2;
assign A1 = (a2&a1&a0&b2&~b1)|(a2&~a1&~a0&b2&~b1);
assign B1 = (~a2&a1&a0&b2&b1)|(a2&a1&b2&b1)|(a2&a0&b2&b1);
assign C1 = (~a2&a1&a0&b2&b1)|(a2&a1&b2&b1)|(a2&~a1&a0&b2);
assign D1 = (a2&~a1&~a0&b2&~b1)|(a2&a1&a0&b2&~b1);
assign E1 = (a2&a1&b2&~b1)|(a2&~a1&~a0&b2&~b1);
assign F1 = (~a2&a1&a0&b2&b1)|(a2&a1&~a0&b2&~b1)|(a2&~a1&b2&~b1);
assign G1 = (~a2&~a1)|(~b2)|(~a2&a1&~a0)|(b2&~b1);
assign A2 = (~a2&~a1&a0)|(~a2&a1&~a0&~b1)|(~b2&~b1)|(a2&~a1&~a0&~b2)|(a2&~a1&~a0&b1);
assign B2 = (a2&~a1&b2&~b1)|(a2&~a1&a0&b1)|(a2&a1&~a0&b1)|(a2&a1&b2&b1)|(a2&a1&~a0&b2);
assign C2 = (~a2&a1&~a0&~b2&b1)|(a2&a1&b2&b1)|(a2&a0&b2&b1);
assign D2 = (~a2&~a1&a0)|(a2&~b2&~b1)|(~b2&~b1)|(~a2&a0&b2)|(a2&a1&a0&~b2)|(a2&a1&a0&~b1)|(a2&~a1&~a0&b1);
assign E2 = (~a2&a0)|(a2&~b2&~b1)|(a2&a0&b2&~b1)|(~a2&a1&b2&~b1)|(a2&~a1&~b2)|(a2&~a1&~a0&b1)|(a2&a0&~b2&b1);
assign F2 = (a2&~b2&~b1)|(~b2&~b1)|(a2&a1&a0&~b2)|(~a2&a0&b1)|(~a2&~a1&a0)|(~a2&a1&~b2);
assign G2 = (~a2&~a1)|(~b2&~b1)|(a2&a1&a0&~b2)|(~a2&a0&b2&b1);
endmodule
6 Replies
Altera_ForumYou didnt post the errors - they will tell you what line of code the error is in.
- Altera_Forum
Also, that code is probably going to use way more FPGA resources than a simple lookup ROM.
- Altera_Forum--- Quote Start --- Also, that code is probably going to use way more FPGA resources than a simple lookup ROM. --- Quote End --- I know but they forbid us to use ROM, they asked us to make it using truth table and deriving the equation using kmap
- Altera_Forum
@Galfonz, probably not. It will simply infer a LUT for each segment, which will in the end be likely not bee all that different from in resource usage than code for a ROM would use. The synthesiser is a smart beast.
@Greital, post the error messages - they will appear in the screen at the bottom of the Quartus window. If you click on the red x button it will filter and show only the errors. https://www.alteraforum.com/forum/attachment.php?attachmentid=11560 - Altera_Forum--- Quote Start --- @Galfonz, probably not. It will simply infer a LUT for each segment, which will in the end be likely not bee all that different from in resource usage than code for a ROM would use. The synthesiser is a smart beast. --- Quote End --- what is LUT :( , I'm pretty new with quartus and all of it things :( , can explain more :) please I checked the error it involve with another files error , can't I analyse&synthesis for each file separately ? and what about the decimal point, what should I do with it to let me access the other segment digit ?? any help :( please
- Altera_Forum
I'm sorry but what is (LUT for each segment) I'm kinda new to quartus and all of its things, so can explain more, please
about the errors I found that they involved with other files error --->> can't I analyse&synthesis for each file alone ??? and what about the decimal point, what should I do with it so I can access the other digit ? and what the code should be written for it in the verilog ? any help :( please
