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Altera_Forum
Honored Contributor
Honored Contributor7segments verilog erorrs
hi, I'm trying to create a verilog file for 2 digit 7 segments, I've created the truth table and derive the equation using kmap but I faced a errors when analyse&synthesis :( the code is : ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- @Galfonz, probably not. It will simply infer a LUT for each segment, which will in the end be likely not bee all that different from in resource usage than code for a ROM would use. The synthesiser is a smart beast. --- Quote End --- what is LUT :( , I'm pretty new with quartus and all of it things :( , can explain more :) please I checked the error it involve with another files error , can't I analyse&synthesis for each file separately ? and what about the decimal point, what should I do with it to let me access the other segment digit ?? any help :( please
