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Altera_Forum
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10 years ago

7segments verilog erorrs

hi, I'm trying to create a verilog file for 2 digit 7 segments, I've created the truth table and derive the equation using kmap but I faced a errors when analyse&synthesis :( the code is : ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Also, that code is probably going to use way more FPGA resources than a simple lookup ROM.