Hello, all.
I attempt to launch the Ethernet 1Gb link through the 1G/10Gbe and 10GBASE-KR PHY Intel Arria 10 FPGA IP.
1Gb patch-cord connects SFP+ port from board with Arria10 with SFP+ port on Mikrotik router.
On Mikrotik SPF+ port Auto-Negotiation is disabled and only speed 1Gb is enabled.
Configuration of 1G/10Gbe and 10GBASE-KR PHY IP is:
IP variant: 1G/10Gb Ethernet
Initial datapath: 1G
tab 10M/100M/1Gb Ethernet -> Enable 1Gb Ethernet protocol = enabled
tab Speed detection -> Enable automatic speed detection = disabled
1G/10Gbe and 10GBASE-KR PHY IP asserts rx_syncstatus and led_link, because accepts BCh 50h pairs.
Router also established link (see attachment).
I see outgoing traffic on the router port.
1. I see ingoing packets (LLDP) on RX on 1G/10Gbe and 10GBASE-KR PHY IP.
I see them on XGMII_RX_DATA[7:0] although I would have expected them on gmii_rx_data since the speed 1Gb is set.
Why used XGMII interface instead of GMII?
2. 1G/10Gbe and 10GBASE-KR PHY IP provides 8bit GMII interface in accordance with documentation.
But I see some changes in XGMII_RX_DATA bits from 8 up to 15.
I know XGMII_RX_DATA[71:0] interface includes data and control for 8 lanes. Each lane consists of 8 bits of data and 1 bit of control.
There are not in the Arria 10 Transceiver PHY documentation the information about this mode of using XGMII interface (when data expected by 8bit GMII interface really transferred by 72bit XGMII interface). Could someone tell me where such usage is described?
3. I performed the following test. Connect the PHY.XGMII_RX_DC to PHY.XGMII_TX_DC (loopback).
But I didn't see the incoming traffic on router port. Why?
Code was started from Intel example:
eth10g_kr_phy phy (
.tx_serial_clk_10g (tx_serial_clk_10g), // 5.156 GHz
.tx_serial_clk_1g (tx_serial_clk_1g), // 625 MHz
.rx_cdr_ref_clk_10g (clk_322),
.rx_cdr_ref_clk_1g (clk_125),
.tx_pma_div_clkout (tx_div_to_xgmii_clk),
.rx_pma_div_clkout (rx_div_to_xgmii_clk),
.xgmii_tx_clk (clk_125), //(clk_156_25), (tx_div_to_xgmii_clk),
.xgmii_rx_clk (clk_125), //(clk_156_25), (tx_div_to_xgmii_clk),
.mode_1g_10gbar (1'b1), // 1 = 1G, 0 = 10G if automatic speed detection is disabled
.tx_clkout (phy_tx_recovered_clk),
.rx_pma_clkout (phy_rx_recovered_clk),
.tx_analogreset (xcvr_reset_control_tx_analogreset[0]),
.tx_digitalreset (xcvr_reset_control_tx_digitalreset[0]),
.rx_analogreset (xcvr_reset_control_rx_analogreset[0]),
.rx_digitalreset (xcvr_reset_control_rx_digitalreset[0]),
// .usr_seq_reset (phy_usr_seq_reset),
.mgmt_clk (csr_clk),
.mgmt_clk_reset (reset),
.mgmt_address (phy_mgmt_address[12:2]),
.mgmt_read (phy_mgmt_read),
.mgmt_readdata (phy_mgmt_readdata),
.mgmt_waitrequest (phy_mgmt_waitrequest),
.mgmt_write (phy_mgmt_write),
.mgmt_writedata (phy_mgmt_writedata),
// GMII
.gmii_tx_d (generated_tx_d), //(phy_xgmii_rx_data), //(mac_gmii_tx_d),
.gmii_tx_en (generated_tx_c), //phy_rx_syncstatus), //(mac_gmii_tx_en),
.gmii_tx_err (mac_gmii_tx_err),
.gmii_rx_d (phy_gmii_rx_d),
.gmii_rx_err (phy_gmii_rx_err),
.gmii_rx_dv (phy_gmii_rx_dv),
.tx_pcfifo_error_1g (phy_tx_pcfifo_error_1g),
.rx_pcfifo_error_1g (phy_rx_pcfifo_error_1g),
.rx_clkslip (phy_rx_clkslip),
// XGMII
.xgmii_tx_dc ({generated_tx_c, generated_tx_d}), //(phy_xgmii_rx_data), // (mac_xgmii_tx_data), loopback RX->TX
.xgmii_rx_dc (phy_xgmii_rx_data),
.rx_is_lockedtodata (xcvr_reset_control_rx_is_lockedtodata[0]),
.tx_cal_busy (xcvr_reset_control_tx_cal_busy[0]),
.rx_cal_busy (xcvr_reset_control_rx_cal_busy[0]),
.rx_data_ready (phy_rx_data_ready),
// PHY Status
.rx_block_lock (rx_block_lock),
.rx_syncstatus (phy_rx_syncstatus),
.led_an (led_an),
.led_char_err (led_char_err),
.led_disp_err (led_disp_err),
.led_link (led_link),
.rx_hi_ber (phy_rx_hi_ber),
// Transceiver Serial Interface
.tx_serial_data (tx_serial_data),
.rx_serial_data (rx_serial_data),
.rx_clkout (),
.tx_pma_clkout (),
.led_panel_link ()
);
// Core PLL
eth10g_core_pll core_pll (
.pll_refclk0 (clk_322),
.pll_powerdown (reset),
.outclk0 (clk_156_25),
.outclk1 (clk_312_5),
.pll_locked (core_pll_locked),
.pll_cal_busy ()
);
// TX PLL for 10G
eth10g_atx_pll atx_pll_10g (
.pll_powerdown (xcvr_reset_control_pll_powerdown), // from reset controller
.pll_refclk0 (clk_322),
.tx_serial_clk (),
.pll_locked (xcvr_reset_control_pll_locked),
.pll_cal_busy (txpll_cal_busy), // to eth10g_channel
.mcgb_rst (xcvr_reset_control_pll_powerdown), // from reset controller
.mcgb_serial_clk (tx_serial_clk_10g) // 5.156 GHz to phy
);
fpll_625 pll_625 (
.pll_refclk0 (clk_125),
.pll_powerdown (reset),
.pll_locked (fpll_625_locked),
.pll_cal_busy (),
.tx_serial_clk (tx_serial_clk_1g) // 625 MHz to phy
);
//=============PHY Reset Controller==========================================
altera_xcvr_reset_controller xcvr_reset_controller (
.clock (csr_clk),
.reset (reset_controller_reset_out),
.pll_powerdown (xcvr_reset_control_pll_powerdown),
.tx_analogreset (xcvr_reset_control_tx_analogreset),
.tx_digitalreset (xcvr_reset_control_tx_digitalreset),
.tx_ready (xcvr_reset_control_tx_ready),
.pll_locked (xcvr_reset_control_pll_locked),
.pll_select (1'b0),
.tx_cal_busy (xcvr_reset_control_tx_cal_busy[0] & txpll_cal_busy),
.rx_analogreset (xcvr_reset_control_rx_analogreset),
.rx_digitalreset (xcvr_reset_control_rx_digitalreset),
.rx_ready (xcvr_reset_control_rx_ready),
.rx_is_lockedtodata (xcvr_reset_control_rx_is_lockedtodata),
.rx_cal_busy (xcvr_reset_control_rx_cal_busy)
);
Thank in advance for help.
Dmitry.
New Contributor
