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DmitryKo's avatar
DmitryKo
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2 years ago

1G/10Gb Ethernet FPGA IP uses XGMII instead of GMII in 1Gb mode

Hello, all. I attempt to launch the Ethernet 1Gb link through the 1G/10Gbe and 10GBASE-KR PHY Intel Arria 10 FPGA IP. 1Gb patch-cord connects SFP+ port from board with Arria10 with SFP+ port on ...
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DmitryKo's avatar
DmitryKo
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2 years ago

Hi, Zying

I use only 8 lowest bits (lane 0) in XGMII tx data bus and 1 next bit (8th) as control bit.
I see the same behavior on xgmii_rx_data: DCh/50h as Idle command is transferred by 8 [7:0] lowest bits, by lane 0 only

But I see some activity on xgmii_rx_data on next 8 bits [16:9]: 95h/04h. In the same time on xgmii_rx_control 1 is present on 0 lane only. From this I can make assumption than these bytes are control bytes. But their values are not understandable.

About this not expected behavior on xgmii bus was may question.

I sent FBh/55h 6 times/D5h before starting packet transfer.

Best regards, Dmitry.