1Dx1D vs 2D matrix, Modelsim error

This is an old problem with the altera tools that I raised back in Quartus 8. The problem is that the BDF files work on the same idea as AHDL rather than anything else, The VHDL conversion is a bit of a fudge. When it does work correctly it actually makes its own 2D version of std_logic, which is really annoying and backwards and no use if you want to interface to it yourself.

The only work around is going to be either write it in VHDL or break the array apart in the schematic. Altera dont really have a lot of interest in fixing the schematic.

Thank you for the replay,

I'm in constant dilemma weather I should scrap using the schematic view or not. It has nice features like when needing to add/change megafunctions etc, but this small thing is really going in my nerves because I need to work on multi-dimensional arrays and I don't like to roll them into std_logic_vector when sending them up to the schematic and then unroll them when I take them back into vhdl...

Also is there any way of opening configuration window on added megafunctions FIFOs etc from vhdl code similar to when I double click the block in schematic?

I'm considering scraping the schematic view, but then I will need to keep the toplevel updated in a design document...

The wizard will generate you a VHDL file and a component declaration you can copy/past into your design. You can use the project navigator window to then double click on a fifo to re-open the megawizard.

But personally I never use the megawizard. If I need a mega function I just instantiate it directly. That way I have much greater control and can use my own generics to re-configer it at compile time. if you go into the help -> contents -> using altera megafunctions -> megafunctions/LPM you get the whole list. In individual megafunctions, parameters are just generics and the rest should be self explanitory.

Edit: I dont like using the megawizard for simple things like altsyncram or dc/scfifo. But for much more complex things like DDR controllers its fine.

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This is an old problem with the altera tools that I raised back in Quartus 8. The problem is that the BDF files work on the same idea as AHDL rather than anything else, The VHDL conversion is a bit of a fudge. When it does work correctly it actually makes its own 2D version of std_logic, which is really annoying and backwards and no use if you want to interface to it yourself.

The only work around is going to be either write it in VHDL or break the array apart in the schematic. Altera dont really have a lot of interest in fixing the schematic.

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It actually is a VHDL limitation where Altera had to work around and thus created the 'in-famous' std_logic_2D to elegantly represent the [][] representation in AHDL.

As we now have VHDL 2008 which allows an unconstrained array of unconstrained std_logic_vector type Altera could easily work around this now.

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It actually is a VHDL limitation where Altera had to work around and thus created the 'in-famous' std_logic_2D to elegantly represent the [][] representation in AHDL.

As we now have VHDL 2008 which allows an unconstrained array of unconstrained std_logic_vector type Altera could easily work around this now.

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But this isnt the bug. The bug is the fact that sometimes, instead of using std_logic_2D, it tries this gem instead for no apparent reason:

input : in std_logic_vector(3 downto 0, 3 downto 0);

Also, I dont know why they couldnt have just used arrays of std_logic_vector to recreate the [][] ability of AHDL. This does mean you have many types flying around, but as you said, VHDL2008 does work better than this. I think in general it shows their lack of interest in supporting the graphic tools.

So everyone needs to lobby Altera to get their act together in supporting 2008.

I agree,

There should be a easy straight forward way of moving from design to simulation.

When I was using Xilinx ISE about a year ago it had a very easy click to move from design and open up waveform window. Did not use schematic files there so there was no issue like this...

Don't take me wrong I really like Quartus tool flow and especially the Timequest tool for timing closure... Only thing missing is this easy link with simulation...

Probably best to stick to the basics and no fancy gui...

Cheers

Just as an asside to this - you may have a better type getting quartus to infer megafunctions rather than dropping them in directly from the megawizard. For example, you get Quartus to infer altsyncrams by using arrays of std_logic_vector/unsigned/signed/integer/sfixed/ufixed and following code guidelines.

See the code guidelines in the Quartus user manual:

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

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But this isnt the bug. The bug is the fact that sometimes, instead of using std_logic_2D, it tries this gem instead for no apparent reason:

input : in std_logic_vector(3 downto 0, 3 downto 0);

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I saw this for the first time today!

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Also, I dont know why they couldnt have just used arrays of std_logic_vector to recreate the [][] ability of AHDL

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Because those arrays of std_logic_vector have fixed dimensions for the std_logic_vector part and that conflicted with the parameters/generics. (That is until VHDL 2008).

I haven't used schematics since the original Quartus (non-II) version where schematic design was somewhat buggy and after a few crashes, loosing my work, I encapsulated it in a AHDL file.

Now I think that schematics would be a nicer way to develop and document at the same time than a VHDL text file full with component declarations, instantiations and the necessary signals to connect everything together.

The schematic editor isn't that bad as quite a few commercial schematic/layout packages do not support double arrays like A[3..0][25..0].

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When I was using Xilinx ISE about a year ago it had a very easy click to move from design and open up waveform window. Did not use schematic files there so there was no issue like this...

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Yet another 'fan' for the internal waveform based simulator.

How do we lobby Altera?