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This is an old problem with the altera tools that I raised back in Quartus 8. The problem is that the BDF files work on the same idea as AHDL rather than anything else, The VHDL conversion is a bit of a fudge. When it does work correctly it actually makes its own 2D version of std_logic, which is really annoying and backwards and no use if you want to interface to it yourself.
The only work around is going to be either write it in VHDL or break the array apart in the schematic. Altera dont really have a lot of interest in fixing the schematic.
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It actually is a VHDL limitation where Altera had to work around and thus created the 'in-famous' std_logic_2D to elegantly represent the [][] representation in AHDL.
As we now have VHDL 2008 which allows an unconstrained array of unconstrained std_logic_vector type Altera could easily work around this now.
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