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It actually is a VHDL limitation where Altera had to work around and thus created the 'in-famous' std_logic_2D to elegantly represent the [][] representation in AHDL.
As we now have VHDL 2008 which allows an unconstrained array of unconstrained std_logic_vector type Altera could easily work around this now.
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But this isnt the bug. The bug is the fact that sometimes, instead of using std_logic_2D, it tries this gem instead for no apparent reason:
input : in std_logic_vector(3 downto 0, 3 downto 0);
Also, I dont know why they couldnt have just used arrays of std_logic_vector to recreate the [][] ability of AHDL. This does mean you have many types flying around, but as you said, VHDL2008 does work better than this. I think in general it shows their lack of interest in supporting the graphic tools.
So everyone needs to lobby Altera to get their act together in supporting 2008.
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