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But this isnt the bug. The bug is the fact that sometimes, instead of using std_logic_2D, it tries this gem instead for no apparent reason:
input : in std_logic_vector(3 downto 0, 3 downto 0);
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I saw this for the first time today!
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Also, I dont know why they couldnt have just used arrays of std_logic_vector to recreate the [][] ability of AHDL
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Because those arrays of std_logic_vector have fixed dimensions for the std_logic_vector part and that conflicted with the parameters/generics. (That is until VHDL 2008).
I haven't used schematics since the original Quartus (non-II) version where schematic design was somewhat buggy and after a few crashes, loosing my work, I encapsulated it in a AHDL file.
Now I think that schematics would be a nicer way to develop and document at the same time than a VHDL text file full with component declarations, instantiations and the necessary signals to connect everything together.
The schematic editor isn't that bad as quite a few commercial schematic/layout packages do not support double arrays like A[3..0][25..0].
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When I was using Xilinx ISE about a year ago it had a very easy click to move from design and open up waveform window. Did not use schematic files there so there was no issue like this...
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Yet another 'fan' for the internal waveform based simulator.
How do we lobby Altera?
Honored Contributor
