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Honored ContributorWorst slack values are Negative for Removal
HI ,
I am trying to run the NIOSII example of led from the nios2 hardware manual.I could generate the nios 2 system.And also integrate it with the Quartus.But when I compile the system in quartus I get the Worst-case Slack values are negative numbers for Removal in Time quest timing Analyser. But the document says that : The Worst-case Slack values are positive numbers for Setup, Hold, Recovery and Removal. If any of these values are negative, the design might not operate properly in hardware. To meet timing, adjust Quartus II assignments to optimize fitting, or reduce the oscillator frequency driving the FPGA. I cant reduce the clock frequency as I using the min freq of 50 Mhz. How to optimise the fitting? I tried to find it but couldnt get it. Can some one explain what the worst slack values for removal means? I also have these critical warnings: Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) Critical Warning: Timing requirements not met Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) Critical Warning: Timing requirements not met Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) Critical Warning: Timing requirements not met :confused: Regards Sneha17 Replies
Altera_ForumRecovery and removal are basically the same as setup and hold, but for asynchronous signals. (At least that's what I learned in my Time Quest lesson, someone correct me if i'm wrong).
I also learned, that you normally don't care about altera_reserved_*, as there's nothing you can do about it.- Altera_Forum
Is the altera_reserved_clk associated with the jtag clk.Because I didnt design it while building the system with SOPC builder.I use only one clk at 50 Mhz.
But I dont know what is this other clk for? I am in the process of reading all the documentation for timing. And it actually is not affecting my design I could successfully download the design and run the code in my hardware. Thanks Again - Altera_Forum
altera_reserved_tck is the JTAG clock and it is present in your system if you use the Nios II debugger, JTAG UART, Signaltap II, etc...
If you select the failing path as shown in Timequest and copy and paste it into a post you'll probably get better information out of us.... - Altera_Forum
Hi,
I am posting the failing path which is in red here. Slow 1200 mV OC model Removal altera_reserved_tck Slack : -2.318 from node: altera_reserved_tck to node : pzdyqx: nabboc|pzdyqx_impl: pzdyqx_impl_inst|FNUJ6967 latch clk : altera_reserved_tck launch clk : altera_reserved_tck 0.000 clk skew: 8.978 data delay: 6.831 -------------same format as above----------- Worst case timing paths: -0.931 altera_reserved_tck pzdyqx: nabboc|pzdyqx_impl: pzdyqx_impl_inst|FNUJ6967 altera_reserved_tck altera_reserved_tck 0.000 4.333 3.486 Summary: altera_reserved_tck slack: -0.931 end point TNS :-0.931 Is this the information which was wanted? The warnings are: Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold) Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold) Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold) System: Info: SRAM Object File D:/altera_VIP/Altera_Demofiles/niosII_hw_dev_tutorial/niosII_hw_dev_tutorial/nios2_quartus2_project_time_limited.sof contains time-limited megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00A2 Info: Started Programmer operation at Thu Apr 07 16:50:34 2011 Error: Can't access JTAG chain Error: Operation failed Info: Ended Programmer operation at Thu Apr 07 16:50:35 2011 Info: Started Programmer operation at Thu Apr 07 16:50:42 2011 Info: Configuring device index 1 Info: Device 1 contains JTAG ID code 0x020F70DD Info: Configuration succeeded -- 1 device(s) configured Info: Successfully performed operation(s) Info: Ended Programmer operation at Thu Apr 07 16:50:49 2011 There I saw that there are 2 errors Regards Sneha - Altera_Forum
That path is the open core plus logic. I have filled a bug against that already since it should constrain itself and since it operates on the slow JTAG clock you can safely ignore it. So if the only failing paths have names like this:
pzdyqx: nabboc|pzdyqx_impl: pzdyqx_impl_inst|FNUJ6967 you can ignore those. So the reason why you are seeing failures is that the logic isn't constrained and not necessarily true failing paths. Unfortunately those are randomized names so you can't add in your own constrains easily. If you were not expecting open core logic in your system then I would look at your licenses and compare against the IP you are using. When you don't have a valid license for an IP block that supports OCP you'll be able to use it in tethered mode (which uses that logic that is showing up in the failing path). - Altera_Forum
Thanks BadOmen,
May be that is the reason I could download the code in the Altera board and also debug the software. The board has been given by university for development purposes and I downloaded the NIOS II and Quartus from the site of Altera. Its a real useful piece of information for me. Special Thanks!! Bye - Altera_Forum
HI,
In the same tutorial I was able to run the code on the leds but the software does not respond to the lcd or the 7 segment display on the board.I dont see the output there though I can see them on the console while debugging Can anyone tell why is this happening? I am using cyclone3 development board.
