Forum Discussion
Altera_Forum
Honored Contributor
15 years agoIs the altera_reserved_clk associated with the jtag clk.Because I didnt design it while building the system with SOPC builder.I use only one clk at 50 Mhz.
But I dont know what is this other clk for? I am in the process of reading all the documentation for timing. And it actually is not affecting my design I could successfully download the design and run the code in my hardware. Thanks Again