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Altera_Forum's avatar
Altera_Forum
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19 years ago

while loops in quartus

Hi there,

Just wondering if anyone out there could help.

I wrote the following code in verilog

r = r-1;

while(r != 0) begin

r = r-1;

end

When I simulate the code in Quartus (web edition) I get the following error:

must use only constant expressions in terminating conditions.

Fair enough. The problem however in my case is that r is a random number (its value is not known in advance)

Can anyone please help me solve this problem. Thanks in advance

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Are you looking to make a test bench or synthesize logic? If it's the latter then I would make sure you know what your synthesis tool will give you. I've seen a few people use loops in their HDL and were surprised by what they ended up with.

    For this reason I never use them. You can transform your HDL easily by just using your "r != 0" as the enable for the registering operation of "r = r - 1". That would give the same sequential behavior you would get out of synthesis. You can go into Quartus and select a template that gives you skeleton code for this type of construct.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    It's really impossible to tell what the problem is without seeing the rest of your code. But what is it you are trying to do? The code you posted appears to neither be useful for simulation or synthesis. You've written a loop that will execute in 0 time. So no matter what r is, it will become 0 in 0 time. Not particularly useful.

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Main issue here is that you think of Verilog as a programming language, which it is not.

    Every line of Verilog is not "executed" by Quartus, but "interpreted" to build a circuit.

    The resulting circuit does not always correspond to the code you wrote line by line, neither is it supposed to, according to the Verilog for Synthesis standard

    Quartus simulator simulates the resulting circuit, not your code. Therefore, you should use Quartus RTL Viewer (Tools->Netlist Viewers->RTL Viewer) to see the circuit that was actually produced, and revise your code to produce the circuit you want.

    I suggest you find a good book that describes Verilog for synthesis. You might want to look up what textbooks good engineering schools use, and go from there.