while loops in quartus

Main issue here is that you think of Verilog as a programming language, which it is not.

Every line of Verilog is not "executed" by Quartus, but "interpreted" to build a circuit.

The resulting circuit does not always correspond to the code you wrote line by line, neither is it supposed to, according to the Verilog for Synthesis standard

Quartus simulator simulates the resulting circuit, not your code. Therefore, you should use Quartus RTL Viewer (Tools->Netlist Viewers->RTL Viewer) to see the circuit that was actually produced, and revise your code to produce the circuit you want.

I suggest you find a good book that describes Verilog for synthesis. You might want to look up what textbooks good engineering schools use, and go from there.