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Altera_Forum
Honored Contributor
Honored Contributorwhile loops in quartus
Hi there, Just wondering if anyone out there could help. I wrote the following code in verilog r = r-1; while(r != 0) begin r = r-1; end When I simulate the code in Quartus...
Altera_ForumHonored Contributor
Honored ContributorIt's really impossible to tell what the problem is without seeing the rest of your code. But what is it you are trying to do? The code you posted appears to neither be useful for simulation or synthesis. You've written a loop that will execute in 0 time. So no matter what r is, it will become 0 in 0 time. Not particularly useful.
