while loops in quartus

Are you looking to make a test bench or synthesize logic? If it's the latter then I would make sure you know what your synthesis tool will give you. I've seen a few people use loops in their HDL and were surprised by what they ended up with.

For this reason I never use them. You can transform your HDL easily by just using your "r != 0" as the enable for the registering operation of "r = r - 1". That would give the same sequential behavior you would get out of synthesis. You can go into Quartus and select a template that gives you skeleton code for this type of construct.