dear all, am using this 64k x 16 Cypress SRAM in my qsys design and able to use my nios code in it. I presume the size of this ram is 1 Mbit ie 128 Kbyte but am able to use only 64 Kbyte of the memory. I am using the IDR71V416 memory available in QSYS lib and changed it to 16 bit address and 16 bit data lines. I observe that its allocating 2^16 address locations with 16 bit data bus but my NIOS code during build shows as if only 64 Kbyte of memory is available. Please help asap. :confused:

The generated interface always presents a byte address. Then, if you use a 16bit wide device without byte enables you must discard A0 and connect Qsys A16-A1 to SRAM A15-A0.

dear mr Cris72 thanks for the reply, I ll try it. The IDR71V416 model is creating byteneable signal also (2^n bits), which i am using as Upper Byte Enable and Lower Byte Enable in my SRAM (CY7C09289V-12AC). What is the logic in using the 16..1 as address line ? Can you explain me better ? I am kind of novice with FPGA. My project offlate demands the usage. Thanks in Advance

Your memory uses 16bit addressing. On the other side Avalon bus uses 8bit addressing, although it can perform 8, 16 or 32bit data access and this is somehow misleading, if you are not aware of it. When Avalon MM accesses consecutive 16bit data, physical addresses are actually multiples of 2 : 0, 2, 4, 6, .... In other words line A0 is used only for 8bit data access. Similarly for 32bit accesses: physical addresses are multiples of 4 : 0, 4, 8, ... and A0,A1 are not used. If your external memory data is 8bit wide, you actually use A0. If your external device is 16bit wide you need to connect the byte enable lines to LB/UB byte select pins of the SRAM, while A0 from Avalon bus is discarded. I'll scratch here an example of how Avalon bus addressing works. 8 bit access address: data 0: 00 1: 01 2: 02 3: 03 4: 04 5: 05 6: 06 7: 07 16 bit access address: data 0: 0100 1: 0100 2: 0302 3: 0302 4: 0504 5: 0504 6: 0706 7: 0706 32 bit access address: data 0: 03020100 1: 03020100 2: 03020100 3: 03020100 4: 07060504 5: 07060504 6: 07060504 7: 07060504

Thanks a lot "Cris72" for your prompt replies, really thankful to u, I have another important doubt !! Can i use the SRAM in AS mode, without programming everytime ? I used to do a Quartus AS mode transfer followed by Flash programmer in NIOS for nios code earlier ! is it same for using SRAM also ? Is the SRAM capable of working as a non-volatile memory ? I want to make the system into a product.

SRAM being a volatile memory, it is definitely not capable of working as a non-volatile memory. Anyway, since you talked about AS configuration and flash, I think you do actually have a non -volatile storage device on your board. If you can load fpga configuration (with AS mode) from this device, sure you can also store Nios code with sram initialization, if this is what you mean with "programming sram every time".

What size is 64K x 16 SRAM ? | Altera Community

12 Replies

Altera_Forum
Honored Contributor
14 years ago
The generated interface always presents a byte address. Then, if you use a 16bit wide device without byte enables you must discard A0 and connect Qsys A16-A1 to SRAM A15-A0.
Altera_Forum
Honored Contributor
14 years ago
dear mr Cris72 thanks for the reply, I ll try it.

The IDR71V416 model is creating byteneable signal also (2^n bits), which i am using as Upper Byte Enable and Lower Byte Enable in my SRAM (CY7C09289V-12AC). What is the logic in using the 16..1 as address line ? Can you explain me better ? I am kind of novice with FPGA. My project offlate demands the usage.

Thanks in Advance
Altera_Forum
Honored Contributor
14 years ago
Your memory uses 16bit addressing. On the other side Avalon bus uses 8bit addressing, although it can perform 8, 16 or 32bit data access and this is somehow misleading, if you are not aware of it.
When Avalon MM accesses consecutive 16bit data, physical addresses are actually multiples of 2 : 0, 2, 4, 6, .... In other words line A0 is used only for 8bit data access.
Similarly for 32bit accesses: physical addresses are multiples of 4 : 0, 4, 8, ... and A0,A1 are not used.
If your external memory data is 8bit wide, you actually use A0.
If your external device is 16bit wide you need to connect the byte enable lines to LB/UB byte select pins of the SRAM, while A0 from Avalon bus is discarded.

I'll scratch here an example of how Avalon bus addressing works.

8 bit access
address: data
0: 00
1: 01
2: 02
3: 03
4: 04
5: 05
6: 06
7: 07

16 bit access
address: data
0: 0100
1: 0100
2: 0302
3: 0302
4: 0504
5: 0504
6: 0706
7: 0706

32 bit access
address: data
0: 03020100
1: 03020100
2: 03020100
3: 03020100
4: 07060504
5: 07060504
6: 07060504
7: 07060504
Altera_Forum
Honored Contributor
14 years ago
Thanks a lot "Cris72" for your prompt replies, really thankful to u, I have another important doubt !! Can i use the SRAM in AS mode, without programming everytime ?

I used to do a Quartus AS mode transfer followed by Flash programmer in NIOS for nios code earlier ! is it same for using SRAM also ? Is the SRAM capable of working as a non-volatile memory ? I want to make the system into a product.
Altera_Forum
Honored Contributor
14 years ago
SRAM being a volatile memory, it is definitely not capable of working as a non-volatile memory.
Anyway, since you talked about AS configuration and flash, I think you do actually have a non -volatile storage device on your board.
If you can load fpga configuration (with AS mode) from this device, sure you can also store Nios code with sram initialization, if this is what you mean with "programming sram every time".
Altera_Forum
Honored Contributor
14 years ago
Hi Cris72, I have FPGA (on chip mem), a EPCS flash memory (I used to flash this memory in AS mode) and a SRAM on my prototype board. Is it possible for me use SRAM as a program memory and store the program in standalone mode ??

I want to use the board as a controller for a project. Please advice what memory i can use ? My string operations in NIOS code are taking up lot of memory so my on-chip mem is not sufficient !!
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Hi Cris72, I have FPGA (on chip mem), a EPCS flash memory (I used to flash this memory in AS mode) and a SRAM on my prototype board. Is it possible for me use SRAM as a program memory and store the program in standalone mode ??

--- Quote End ---

Sure you can!
I sketch here the epcs programming procedure.
Browse the Altera documentation or search the forum for detailed information.

Say fpga.sof is your fpga configuration file and nios.elf the nios firmware.
First of all open a Nios command shell session.
Convert sof file into hex:
sof2flash --epcs --input=fpga.sof --output=fpga.flash
Convert elf file into hex and remap data just after fpga configuration
elf2flash --epcs --after=fpga.flash --input=nios.elf --output=nios.flash
Configure fpga, in order to be able to access epcs for programming
nios2-configure-sof nios.sof
Program epcs:
nios2-flash-programmer --epcs --base=0x100000 fpga.flash
nios2-flash-programmer --epcs --base=0x100000 nios.flash
(Important: replace the fake address 0x100000 with your actual epcs base address, as defined in Qsys)

That's all. The next time you power up the board, it will work standalone.:)

--- Quote Start ---

I want to use the board as a controller for a project. Please advice what memory i can use ? My string operations in NIOS code are taking up lot of memory so my on-chip mem is not sufficient !!
--- Quote End ---

You can use sram for program code, data, stack or any memory section you want. You select this in bsp properties.
Please note that SRAM is far more slow than on-chip memory, because of longer access times and half data width (two cycles are required for every 32bit access). So you'd better place there only non-critical code and/or data not frequently accessed. This would be an issue only if your project has great performance requirements.

Regards
Cris
Altera_Forum
Honored Contributor
14 years ago
Thanks Cris72, I ll give it a shot.. i am really happy that i could get replies so fast over the forum. thanks cris for that again.
Altera_Forum
Honored Contributor
14 years ago
Hi all,

I am getting my quartus code (.sof) flashed correctly using the NIOS II IDE 11.1 - Flash programmer. But the nios code is not getting flashed.

i am getting the following warning in problems tab -

"WARNING: The expected CPU name does not match the selected target CPU name."

and am getting the following messages in processing tab

Info: Info: *******************************************************************
Info: Info: Running Quartus II 32-bit Convert_programming_file
Info: Info: Command: quartus_cpf --no_banner --convert --device=EPCS128 --option=flash/rpctrl_epcs_flash_controller_0.opt G:/rp_ctrl/rpctrl_q101/rpctrl/rpctrl.sof flash/rpctrl_epcs_flash_controller_0.pof
Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings
Info: Info: Peak virtual memory: 150 megabytes
Info: Info: Processing ended: Fri Jan 20 10:53:36 2012
Info: Info: Elapsed time: 00:00:05
Info: Info: Total CPU time (on all processors): 00:00:06
Info: Info: *******************************************************************
Info: Info: Running Quartus II 32-bit Convert_programming_file
Info: Info: Command: quartus_cpf --no_banner --convert flash/rpctrl_epcs_flash_controller_0.pof flash/rpctrl_epcs_flash_controller_0.rpd
Info: Info: Quartus II 32-bit Convert_programming_file was successful. 0 errors, 0 warnings
Info: Info: Peak virtual memory: 144 megabytes
Info: Info: Processing ended: Fri Jan 20 10:53:40 2012
Info: Info: Elapsed time: 00:00:03
Info: Info: Total CPU time (on all processors): 00:00:04
Info: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Info: Resetting and pausing target processor: OK
Info: Reading System ID at address 0x000818E8: verified
Info:
Info: : Checksumming existing contents
Info:
Info: 00000000 : Verifying existing contents
Info:
Info: 00010000 : Verifying existing contents
Info:
Info: 00020000 : Verifying existing contents
Info:
Info: 00030000 : Verifying existing contents
Info:
Info: 00040000 : Verifying existing contents
Info:
Info: 00050000 : Verifying existing contents
Info:
Info: 00060000 : Verifying existing contents
Info:
Info: 00070000 : Verifying existing contents
Info:
Info: 00080000 : Verifying existing contents
Info:
Info: 00090000 : Verifying existing contents
Info:
Info: 000A0000 : Verifying existing contents
Info:
Info: 000B0000 : Verifying existing contents
Info:
Info: 00000000 : Reading existing contents
Info:
Info: 00010000 : Reading existing contents
Info:
Info: 00020000 : Reading existing contents
Info:
Info: 00030000 : Reading existing contents
Info:
Info: 00040000 : Reading existing contents
Info:
Info: 00050000 : Reading existing contents
Info:
Info: 00060000 : Reading existing contents
Info:
Info: 00070000 : Reading existing contents
Info:
Info: 00080000 : Reading existing contents
Info:
Info: 00090000 : Reading existing contents
Info:
Info: 000A0000 : Reading existing contents
Info:
Info: 000B0000 : Reading existing contents
Info:
Info: Checksummed/read 44kB in 1.6s
Info:
Info: 00000000 ( 0%): Erasing
Info:
Info: 00010000 ( 8%): Erasing
Info:
Info: 00020000 (16%): Erasing
Info:
Info: 00030000 (25%): Erasing
Info:
Info: 00040000 (33%): Erasing
Info:
Info: 00050000 (41%): Erasing
Info:
Info: 00060000 (50%): Erasing
Info:
Info: 00070000 (58%): Erasing
Info:
Info: 00080000 (66%): Erasing
Info:
Info: 00090000 (75%): Erasing
Info:
Info: 000A0000 (83%): Erasing
Info:
Info: 000B0000 (91%): Erasing
Info:
Info: Erased 768kB in 7.6s (101.0kB/s)
Info:
Info: 00000000 ( 0%): Programming
Info:
Info: 00010000 ( 8%): Programming
Info:
Info: 00020000 (16%): Programming
Info:
Info: 00030000 (25%): Programming
Info:
Info: 00040000 (33%): Programming
Info:
Info: 00050000 (41%): Programming
Info:
Info: 00060000 (50%): Programming
Info:
Info: 00070000 (58%): Programming
Info:
Info: 00080000 (66%): Programming
Info:
Info: 00090000 (75%): Programming
Info:
Info: 000A0000 (83%): Programming
Info:
Info: 000B0000 (91%): Programming
Info:
Info: Programmed 725KB +43KB in 18.7s (41.0KB/s)
Info: Did not attempt to verify device contents
Info: Leaving target processor paused
Info: Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Info: Resetting and pausing target processor: OK
Info: Reading System ID at address 0x000818E8: verified
Info:
Info: : Checksumming existing contents
Info:
Info: 000B0000 : Verifying existing contents
Info:
Info: 000C0000 : Verifying existing contents
Info:
Info: 000B0000 : Reading existing contents
Info:
Info: 000C0000 : Reading existing contents
Info:
Info: Checksummed/read 58kB in 1.7s
Info:
Info: 000B0000 ( 0%): Erasing
Info:
Info: 000C0000 (50%): Erasing
Info:
Info: Erased 128kB in 1.3s (98.4kB/s)
Info:
Info: 000B0000 ( 0%): Programming
Info:
Info: 000C0000 (50%): Programming
Info:
Info: Programmed 71KB +57KB in 2.1s (60.9KB/s)
Info: Did not attempt to verify device contents
Info: Leaving target processor paused

I am testing with a Char LCD code.. i am not getting the processor to start. I have tested the same code with SRAM and On-Chip memory for the program memory, same result

Please help.
Altera_Forum
Honored Contributor
14 years ago
Did you use the instructions I posted before or did you use the Flash programmer in the IDE?

Forum Discussion

What size is 64K x 16 SRAM ?

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