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Altera_Forum
Honored Contributor
14 years agodear mr Cris72 thanks for the reply, I ll try it.
The IDR71V416 model is creating byteneable signal also (2^n bits), which i am using as Upper Byte Enable and Lower Byte Enable in my SRAM (CY7C09289V-12AC). What is the logic in using the 16..1 as address line ? Can you explain me better ? I am kind of novice with FPGA. My project offlate demands the usage. Thanks in Advance