What size is 64K x 16 SRAM ?

Your memory uses 16bit addressing. On the other side Avalon bus uses 8bit addressing, although it can perform 8, 16 or 32bit data access and this is somehow misleading, if you are not aware of it.

When Avalon MM accesses consecutive 16bit data, physical addresses are actually multiples of 2 : 0, 2, 4, 6, .... In other words line A0 is used only for 8bit data access.

Similarly for 32bit accesses: physical addresses are multiples of 4 : 0, 4, 8, ... and A0,A1 are not used.

If your external memory data is 8bit wide, you actually use A0.

If your external device is 16bit wide you need to connect the byte enable lines to LB/UB byte select pins of the SRAM, while A0 from Avalon bus is discarded.

I'll scratch here an example of how Avalon bus addressing works.

8 bit access

address: data

0: 00

1: 01

2: 02

3: 03

4: 04

5: 05

6: 06

7: 07

16 bit access

address: data

0: 0100

1: 0100

2: 0302

3: 0302

4: 0504

5: 0504

6: 0706

7: 0706

32 bit access

address: data

0: 03020100

1: 03020100

2: 03020100

3: 03020100

4: 07060504

5: 07060504

6: 07060504

7: 07060504