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SKuma36's avatar
SKuma36
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7 years ago

We are not getting proper data when we do a read access to the on-chip memory via the AXI interface.

Hi,

We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Processor via AHB slave interface. The AXI master interface is connected to the the on-chip memory which is accessed by NIOS II processor also. We are not getting proper data when we do a read access to the on-chip memory via the AXI interface. Could you pl. suggest how to debug this?

thanks,

sunil

23 Replies

  • KennyT_altera's avatar
    KennyT_altera
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    7 years ago

    Thanks for your screenshot attached,

    can you remove the AXI interface first and check on the signal tap? This will help to narrow down whether the problem is coming from the AXI.

    • SKuma36's avatar
      SKuma36
      Icon for Occasional Contributor rankOccasional Contributor
      7 years ago

      Hi,

      Our controller has both AHB slave as well as AXI Master interface. So the bridge component that we created in the QSYS system has both AHB and AXI interfaces.

      AHB interface is used to access our Controller’s internal registers from NIOS II processor. AXI interface is used to access the on-chip memory from our controller

      AHB interface works fine, we are able to read/write to our Controller’s internal registers from NIOS II processor. The issue is seen with AXI interface, when we do a read access to on-chip memory from our controller, we are not getting back the data properly.

      So removing the bridge will not help in our testing. Do you have any other suggestion on how to connect the AXI interface form our controller to the Avalon interface of the on-chip memory?

      Rgds,

      sunil

  • KennyT_altera's avatar
    KennyT_altera
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    7 years ago

    Can u send us some screenshot on the failure? Where do you see the improper data when u read access the on chip ram.

  • SKuma36's avatar
    SKuma36
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    Hi, I've attached the QSYS connectivity details, SOPCINFO file and SignalTap snapshot file showing the read access from the onchip memory via AXI interface. Also I have shared below the code snippet used for onchip memory write. In the SignalTap snapshot, you can see we are receiving same data (E5F6A2B3A1B2C3D4) for two clock cycles. But the expected data is E5F6A2B3A1B2C3D4 and A3B4C5D6C4D5E6F7. Code snippet: //ON-CHIP Memory write temp=0x1000; IOWR_32DIRECT(0x00000000,temp,0xa1b2c3d4); temp=0x1004; IOWR_32DIRECT(0x00000000,temp,0xe5f6a2b3); temp=0x1008; IOWR_32DIRECT(0x00000000,temp,0xc4d5e6f7); temp=0x100c; IOWR_32DIRECT(0x00000000,temp,0xa3b4c5d6); rgds, sunil
  • KennyT_altera's avatar
    KennyT_altera
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    7 years ago

    Did you attached the signal tap snapshot? I cant see it from my side. Btw, you have all your timing close right?

    • SKuma36's avatar
      SKuma36
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      7 years ago

      SignalTap snapshot attached...yes, the bitstream is timing closed.​

  • SKuma36's avatar
    SKuma36
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    7 years ago
    Hi, PFA the SignalTap snapshot. BTW, the bitstream is timing closed. Also I have shared the QSYS connectivity diagram. Could you pl. check and confirm if the connections are fine? Rgds, sunil
  • KennyT_altera's avatar
    KennyT_altera
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    7 years ago

    I did not receive any diagram from the Qsys, I have send you the request seperately, you can check your inbox.

    • SKuma36's avatar
      SKuma36
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      7 years ago

      Attached snapshot of QSYS system connectivity diagram....​

  • SKuma36's avatar
    SKuma36
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    7 years ago
    Hi, How do I share the files? Do I need to reply to this mail or login to community forums? Rgds, sunil
  • SKuma36's avatar
    SKuma36
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    Hi, I have attached the following files along with this mail. Pl. check if you are able to receive it. 1. SOPCINFO file 2. SignalTap snapshot 3. Qsys system connectivity diagram Rgds, sunil
  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    Also, why do you want to add an AXI bridge? Both of the NIOS and RAM are using the avalon interface.