Forum Discussion
SKuma36
Occasional Contributor
7 years agoHi,
I've attached the QSYS connectivity details, SOPCINFO file and SignalTap snapshot file showing the read access from the onchip memory via AXI interface. Also I have shared below the code snippet used for onchip memory write.
In the SignalTap snapshot, you can see we are receiving same data (E5F6A2B3A1B2C3D4) for two clock cycles. But the expected data is E5F6A2B3A1B2C3D4 and A3B4C5D6C4D5E6F7.
Code snippet:
//ON-CHIP Memory write
temp=0x1000;
IOWR_32DIRECT(0x00000000,temp,0xa1b2c3d4);
temp=0x1004;
IOWR_32DIRECT(0x00000000,temp,0xe5f6a2b3);
temp=0x1008;
IOWR_32DIRECT(0x00000000,temp,0xc4d5e6f7);
temp=0x100c;
IOWR_32DIRECT(0x00000000,temp,0xa3b4c5d6);
rgds,
sunil