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SKuma36
Occasional Contributor
Occasional ContributorWe are not getting proper data when we do a read access to the on-chip memory via the AXI interface.
Hi, We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Process...
SKuma36Occasional Contributor
Occasional ContributorHi,
PFA the SignalTap snapshot. BTW, the bitstream is timing closed.
Also I have shared the QSYS connectivity diagram. Could you pl. check and confirm if the connections are fine?
Rgds,
sunil
