Forum Discussion
SKuma36
Occasional Contributor
Occasional ContributorWe are not getting proper data when we do a read access to the on-chip memory via the AXI interface.
Hi, We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Process...
KennyT_altera
Super Contributor
Super ContributorDid you attached the signal tap snapshot? I cant see it from my side. Btw, you have all your timing close right?
SKuma36SignalTap snapshot attached...yes, the bitstream is timing closed.
