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SKuma36's avatar
SKuma36
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

We are not getting proper data when we do a read access to the on-chip memory via the AXI interface.

Hi, We are using Arria10 FPGA to implement our custom IP controller. The controller has both AHB slave as well as AXI master interfaces. The controller's registers are accessed using NIOS II Process...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 years ago

Did you attached the signal tap snapshot? I cant see it from my side. Btw, you have all your timing close right?

  • SKuma36's avatar
    SKuma36
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    SignalTap snapshot attached...yes, the bitstream is timing closed.​